Typical semiconductor memory utilized during microprocessor operation is volatile. That is in the case of power interruption, the data stored in the semiconductor memory is typically completely lost. One way to circumvent this problem is to provide separate backup of the memory, such as battery power or capacitor storage. An alternate technique would be to make the memory fundamentally non-volatile. This option is highly desirable because non-volatile semiconductor memories would not only withstand power interruption, but also would be stored or shipped without being energized.
Typical prior art non-volatile memory cells are charge-trapping devices. Examples includes floating-gate memory devices wherein charge is stored in an isolated conductor, commonly referred to as a "floating-gate", in a field effective transistor (FET) device. Other charge-storage devices are constructed to store charge in insulator bulk traps in FET constructions. Examples includes metal-nitride-oxide-semiconductor (MNOS); metal-alumina-oxide-semiconductor (MAOS); metal-alumina-semiconductor (MAS); and silicon-oxide-nitride-oxide-semiconductor (SONOS) memory cells. This invention is specific to SONOS memory technology.
SONOS technology has existed since the late 1960's, but has not been widely used because of other apparent fundamental problems, such as data retention, process control issues, etc. Drawbacks of non-volatile semiconductor memories, such as SONOS cells, includes process complexity and cell size in comparison with a more conventional volatile dynamic random access memory (DRAM) type memory cell. Virtual ground architecture has been used in SONOS memories to reduce cell size to near theoretical limits. The use of SONOS with virtual ground has, however, been limited by the technological problems described above and by charge-disturb problems.
FIG. 1 shows a prior art circuit schematic for a SONOS virtual ground array of cells, while FIGS. 2 and 3 illustrate a top and sectional cut, respectively, of a portion of the FIG. 1 virtual ground SONOS array. FIG. 1 illustrates four SONOS memory cells 10, 11, 12 and 13, each consisting of a single SONOS memory transistor. Looking specifically to transistor 10, such is comprised of a bulk substrate portion 14 and includes a pair of source/drain diffusion regions 15, 16, a gate dielectric layer 17 and a polysilicon gate 18. Substrate 14 would be of a semiconductor material, typically comprising silicon, while dielectric region 17 would be formed of an oxide-nitride-oxide (ONO) construction. Thus, in combination with the polysilicon of gate 18, a silicon-oxide-nitride-oxide-semiconductor (SONOS) transistor is provided. Field oxide regions 19 and 20 and adjacent insulating oxide regions 21 and 22 provide electrical isolation from adjoining devices. An overlying polysilicon word line 23 provides electrical connection to gate 18.
Many memory cells, including some non-volatile memory cells, enable sharing of source/drain diffusion regions among an adjacent pair of transistors. This enables increased circuit density. Such sharing is not, however, possible with the illustrated virtual ground SONOS cell because of the need for isolated source/drain diffusion areas between adjacent transistors. Specifically, adjacent SONOS transistors 10 and 11 require separate and electrically isolated adjacent bit lines 24 and 25.
Because of this isolated source/drain requirement, the virtual ground SONOS cell size is significantly larger when compared to other memories. Specifically referring to FIG. 3, the length direction of the cell consists of one isolation space, two diffusions, and a gate resulting in a length of four times the minimum photolithographic masking feature size, which is referred to in FIG. 3 as .lambda.. Accordingly, the maximum length dimension of the illustrated cell is 4.lambda., providing a cell area of 8.lambda..sup.2. On the other hand, a typical floating-gate non-volatile memory cell has a theoretical cell size of 4.lambda..sup.2, again where .lambda. is the minimum lithographic feature size.
Certain SONOS and MNOS memory cells have been constructed which enable sharing of source/drain diffusion regions between adjacent transistors. Such a construction does, however, require an additional transistor, referred to as a "select transistor", to prevent charge stored in the oxide-nitride-oxide from being disturbed. An example of such
prior art is shown by Nozaki et al., "A 1-Mb EEPROM With MONOS Memory Cell For Semiconductor Disk Application", IEEE Journal Of Solid-State Circuits, Vol. 26, No. 4, pp. 497-501 (April 1991).